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| BR24G32-3A datashee t product structure silicon monolithic integrated circuit this product is not designed protection against radioactive rays . 1/34 tsz02201-0r2r0g100050 -1-2 15.may.2012 rev.001 ? 2012 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 14 ? 001 high reliability serial eeproms i 2 c bus br24xxxxfamily BR24G32-3A general description br24g32 - 3a is a serial eeprom of i 2 c bus interface method features ? all controls available by 2 ports of serial clock(scl) and serial data(sda) ? other devices than eeprom can be connected to the same port, saving microcontroller port ? 1.7v to 5.5v single power source action most suitable for battery use ? 1.7v to 5.5 wide limit of action voltage, possible 1mhz action ? page write mode useful for in itial value write at factory shipment ? auto erase and auto end function at data rewrite ? low current consumption ? write mistake prevention function ? write (write protect) function added ? write mistake prevention function at low voltage ? data rewrite up to 1,000,000 times ? data kept for 40 years ? noise filter built in scl / sda terminal ? shipment data all address ffh page write number of pages 32byte product number BR24G32-3A BR24G32-3A capacity bit format type power source voltage dip-t8 *1 sop8 sop-j8 ssop-b8 tssop-b8 tssop-b8j msop8 vson008 x2030 32kbit 4k8 BR24G32-3A 1.7 to 5.5v packages w(typ.) x d(typ.)x h(max.) msop8 2.90mm x 4.00mm x 0.90mm sop-j8 4.90mm x 6.00mm x 1.65mm sop8 5.00mm x 6.20mm x 1.71mm dip-t8 9.30mm x 6.50mm x 7.10mm ssop-b8 3.00mm x 6.40mm x 1.35mm tssop-b8 3.00mm x 6.40mm x 1.20mm tssop-b8j 3.00mm x 4.90mm x 1.10mm v son008x2030 2.00mm x 3.00mm x 0.60mm fig.1 *1 dip-t8 is not halogen free package
2/34 datasheet d a t a s h e e t BR24G32-3A ? 2012 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100050 -1-2 15.may.2012 rev.001 absolute maximum ratings (ta=25 ) parameter symbol ratings unit remarks impressed voltage v cc -0.3 to +6.5 v 450 (sop8) when using at ta=25 or higher 4.5mw to be reduced per 1 . 450 (sop-j8) when using at ta=25 or higher 4.5mw to be reduced per 1 . 300 (ssop-b8) when using at ta=25 or higher 3.0mw to be reduced per 1 . 330 (tssop-b8) when using at ta=25 or higher 3.3mw to be reduced per 1 . 310 (tssop-b8j) when using at ta=25 or higher 3.1mw to be reduced per 1 . 310 (msop8) when using at ta=25 or higher 3.1mw to be reduced per 1 . 300 (vson008x2030) when using at ta=25 or higher 3.0mw to be reduced per 1 . permissible dissipation pd 800 (dip-t8) mw when using at ta=25 or higher 8.0mw to be reduced per 1 . storage temperature range ts t g 65 to +150 action temperature range topr 40 to +85 terminal voltage \ -0.3 to vcc+1.0 v the max value of terminal voltage is not over 6.5v. when the pulse width is 50ns or less, the min value of terminal voltage is not under -1.0v. junction temperature tjmax 150 junction temperature at the storage condition memory cell characteristics (ta=25 , vcc=1.7v to 5.5v) limits parameter min. typ. max unit number of data rewrite times *1 1,000,000 times data hold years *1 40 years *1not 100% tested recommended operating ratings parameter symbol ratings unit power source voltage vcc 1.7 to 5.5 input voltage v in 0 to vcc v electrical characteristics (unless otherwise specified, ta=-40 to +85 , vcc =1.7 to 5.5v) limits parameter symbol min. typ. max. unit conditions ?h? input voltage 1 v ih1 0.7vcc vcc+1.0 v ?l? input voltage 1 v il1 0.3 *1 0.3vcc v ?l? output voltage 1 v ol1 0.4 v i ol =3.0ma, 2.5v Q vcc Q 5.5v (sda) ?l? output voltage 2 v ol2 0.2 v i ol =0.7ma, 1.7v Q vcc 2.5v (sda) input leak current i li 1 1 a v in =0 to vcc output leak current i lo 1 1 a v out =0 to vcc (sda) i cc1 2.5 vcc=5.5v,f scl =1mhz, t wr =5ms, byte write, page write current consumption at action i cc2 - - 2.0 ma vcc=5.5v,f scl =1mhz random read, current read, sequential read standby current i sb 2.0 a vcc=5.5v, sda, scl=vcc a0, a1, a2=gnd,wp=gnd *1 when the pulse width is 50ns or less, it is -1.0v. 3/34 datasheet d a t a s h e e t BR24G32-3A ? 2012 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100050 -1-2 15.may.2012 rev.001 action timing characteristics (unless otherwise specified, ta= 40 to +85 , v cc =1.7v to 5.5v) limits parameter symbol min. typ. max. unit clock frequency fscl 1000 khz data clock ?high? period thigh 0.30 s data clock ?low? period tlow 0.5 s sda, scl (input) rise time *1 tr 0.12 s sda, scl (input) fall time *1 tf1 0.12 s sda (output) fall time *1 tf2 0.12 s start condition hold time thd:sta 0.25 s start condition setup time tsu:sta 0.25 s input data hold time thd:dat 0 ns input data setup time tsu:dat 50 ns output data delay time tpd 0.05 0.45 s output data dold time tdh 0.05 s stop condition setup time tsu:sto 0.25 s bus free time tbuf 0.5 s write cycle time twr 5 ms noise spike width (sda, scl) ti 0.05 s wp hold time thd:wp 1.0 s wp setup time tsu:wp 0.1 s wp high period thigh:wp 1.0 s *1 not 100% tested action timing characteristics condition parameter symbol condition unit load capacitance cl 100 pf sda, scl (input) rise time tr 20 ns sda, scl (input) fall time tf1 20 ns input data level vil1/vih1 0.2vcc/0.8vcc v input/output data timing reference level - 0.3vcc/0.7vcc v 4/34 datasheet d a t a s h e e t BR24G32-3A ? 2012 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100050 -1-2 15.may.2012 rev.001 sync data input / output timing fig.2-(e) wp timing at write cancel fig.2-(d) wp timing at write execution fig.2-(c) write cycle timing fig.2-(b) start-stop bit timing fig.2-(a) sync data input / output timing input read at the rise edge of scl data output in sync with the fall of scl scl sda ( ) sda ( ) tr tf1 thigh tsu:dat tlow thd:dat tdh tpd tbuf thd:sta 70% 30% 70% 70% 30% 70% 70% 30% 30% 70% 70% 30% 70% 70% 70% 70% 30% 30% 30% 30% tf2 70% 70% tsu:sta thd:sta start condition tsu:sto stop condition 30% 30% 70% 70% d0 ack twr write data (n-th address) start condition stop condition 70% 70% data(1) d0 ack d1 data(n) ack twr 30% 70% stop condition thd:wp tsu:wp 30% 70% data(1) d0 d1 ack data(n) ack thigh:wp 70% 70% twr 70% (input) (output) 5/34 datasheet d a t a s h e e t BR24G32-3A ? 2012 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100050 -1-2 15.may.2012 rev.001 block diagram fig.3 block diagram pin configuration pin description function terminal name input/ output BR24G32-3A a0 input slave address setting a1 input slave address setting a2 input slave address setting gnd reference voltage of all input / output, 0v sda input/ output serial data input serial data output scl input serial clock input wp input write protect terminal vcc connect the power source. 1 1 1 2 1 3 1 4 1 1 6 1 5 BR24G32-3A a0 1 7 a1 a2 gnd vcc wp scl 8 sda 8 7 6 5 4 3 2 1 sda scl wp v cc gnd a2 a1 a0 address decoder word address register data register control circuit high voltage generating circuit power source voltage detection 8bit ack start stop 32kbit eeprom array 12bit 6/34 datasheet d a t a s h e e t BR24G32-3A ? 2012 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100050 -1-2 15.may.2012 rev.001 typical performance curves fig.4 'h' input voltage vih1 (a0,a1,a2,scl,sda,wp) fig.5 'l' input voltage vil1 (a0,a1,a2,scl,sda,wp) fig. 6 'l' output voltage v ol1 (vcc=2.5v) fig.7 'l' output voltage v ol2 (vcc=1.7v) 0 1 2 3 4 5 6 0123456 supply voltage: vcc(v) l input voltage: v il1 (v) ta=-40 ta= 25 ta= 85 spec 0 1 2 3 4 5 6 0123456 supply voltage: vcc(v) h input voltage: v ih1 (v) ta=-40 ta= 25 ta= 85 spec 0 0.2 0.4 0.6 0.8 1 0123456 l output current: i ol (ma) l output voltage: v ol2 (v) spec ta=-40 ta= 25 ta= 85 0 0.2 0.4 0.6 0.8 1 0123456 l output current: i ol (m a) l output voltage: v ol1 (v) ta=-40 ta= 25 ta= 85 spec 7/34 datasheet d a t a s h e e t BR24G32-3A ? 2012 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100050 -1-2 15.may.2012 rev.001 typical performance curves \ continued fig.8 input leak current i li (a0,a1,a2,scl,wp) fig.9 output leak current i lo (sda) fig.10 current consumption at write operation icc1 fig. 11 current consumption at read operation i cc2 (fscl=1mhz) 0 0.2 0.4 0.6 0.8 1 1.2 0123456 supply voltage: vcc(v) input leak current: i li (a) ta=-40 ta= 25 ta= 85 spec 0 0.2 0.4 0.6 0.8 1 1.2 0123456 supply voltage: vcc(v) output leak current: i lo (a) ta=-40 ta= 25 ta= 85 spec 0 0.5 1 1.5 2 2.5 3 0123456 supply voltage: vcc(v) current consumption at writing: icc1(ma) ta=-40 ta= 25 ta= 85 spec 0 0.5 1 1.5 2 2.5 0123456 supply voltage: vcc(v) current consumption at reading: icc2(ma) spec ta=-40 ta= 25 ta= 85 8/34 datasheet d a t a s h e e t BR24G32-3A ? 2012 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100050 -1-2 15.may.2012 rev.001 typical performance curves \ continued fig.12 standby operation i sb fig.13 clock frequency f scl fig.14 data clock high period t high fig.15 data clock low period t low 0.1 1 10 100 1000 10000 0123456 supply voltage: vcc(v) scl frequency: fscl(khz) spec ta=-40 ta= 25 ta= 85 0 0.1 0.2 0.3 0.4 0123456 su ppl y vol tage: vcc(v) data clk h time : t high (s) spec ta=-40 ta= 25 ta= 85 0 0.1 0.2 0.3 0.4 0.5 0.6 0123456 supply voltage: vcc(v) data clk l time : t low (s) spec ta=-40 ta= 25 ta= 85 0 0.5 1 1.5 2 2.5 0123456 supply voltage: vcc(v) standby current: i sb (a) spec ta=-40 ta= 25 ta= 85 9/34 datasheet d a t a s h e e t BR24G32-3A ? 2012 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100050 -1-2 15.may.2012 rev.001 typical performance curves \ continued fig.17 start condition hold time t hd : sta fig.16 sda (output) fall time t f2 fig.18 start condition setup time t su : sta 0 0.05 0.1 0.15 0.2 0.25 0.3 0123456 supply voltage: vcc(v) start condition hold time: t hd:sta (s) spec ta=-40 ta= 25 ta= 85 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0123456 supply voltage: vcc(v) sda (output) fall time: t f2 (s) spec ta=-40 ta= 25 ta= 85 0 0.05 0.1 0.15 0.2 0.25 0.3 0123456 supply voltage: vcc(v) start condition set up time: t su:sta (s) spec ta=-40 ta= 25 ta= 85 fig.19 input data hold time t hd : dat(high) -150 -100 -50 0 50 0123456 supply voltage: vcc(v) input data hold time: t hd:dat (ns) spec ta=-40 ta= 25 ta= 85 10/34 datasheet d a t a s h e e t BR24G32-3A ? 2012 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100050 -1-2 15.may.2012 rev.001 typical performance curves \ continued -150 -100 -50 0 50 0123456 supply voltage: vcc(v) input data hold time: t hd:dat (ns) spec ta=-40 ta= 25 ta= 85 0 10 20 30 40 50 60 0123456 supply voltage: vcc(v) input data set up time: t su:dat (ns) spec ta=-40 ta= 25 ta= 85 0 10 20 30 40 50 60 0123456 supply voltage: vcc(v) input data set up time: t su:dat (ns) spec ta=-40 ta= 25 ta= 85 0 0.1 0.2 0.3 0.4 0.5 0123456 supply voltage: vcc(v) output data delay time: t pd (s) spec spec ta=-40 ta= 25 ta= 85 fig.20 input data hold time t hd : dat(low) fig.21 input data setup time t su : dat(high) fig.22 input data setup time t su : dat(low) fig.23 output data delay time t pd0 11/34 datasheet d a t a s h e e t BR24G32-3A ? 2012 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100050 -1-2 15.may.2012 rev.001 typical performance curves \ continued 0 0.1 0.2 0.3 0.4 0.5 0123456 supply voltage: vcc(v) output data delay time: t pd (s) spec spec ta=-40 ta= 25 ta= 85 0 0.05 0.1 0.15 0.2 0.25 0.3 0123456 supply voltage: vcc(v) stop condition set up time: t su:sto (s) spec ta=-40 ta= 25 ta= 85 0 0.1 0.2 0.3 0.4 0.5 0.6 0123456 su ppl y vol tage: vcc(v) bus open time before transmission : t buf (s) spec ta=-40 ta= 25 ta= 85 0 1 2 3 4 5 6 0123456 supply voltage: vcc(v) internal writing cycle time: t wr (ms) ta=-40 ta= 25 ta= 85 spec fig.26 bus free time t buf fig.24 output data delay time t pd1 fig.25 stop condition setup time t su:sto fig.27 write cycle time t wr 12/34 datasheet d a t a s h e e t BR24G32-3A ? 2012 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100050 -1-2 15.may.2012 rev.001 fig. 31 noise spike width t l (sda l) fig. 30 noise spike width t l (sda h) fig. 29 noise spike width t l (sc l l) fig. 28 noise spike width t l (sc l h) typical performance curves \ continued 0 0.05 0.1 0.15 0.2 0.25 0.3 0123456 supply voltage: vcc(v) noise reduction efective time: ti(scl l)(s ) spec ta=-40 ta= 25 ta= 85 0 0.05 0.1 0.15 0.2 0.25 0.3 0123456 supply voltage: vcc(v) noise reduction efective time: ti(scl h)(s) spec ta=-40 ta= 25 ta= 85 0 0.05 0.1 0.15 0.2 0.25 0.3 0123456 supply voltage: vcc(v) noise reduction efective time: t i (sda l)(s) spec ta=-40 ta= 25 ta= 85 0 0.05 0.1 0.15 0.2 0.25 0.3 0123456 supply voltage: vcc(v) noise reduction efective time: t i (sda h)(s) spec ta=-40 ta= 25 ta= 85 13/34 datasheet d a t a s h e e t BR24G32-3A ? 2012 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100050 -1-2 15.may.2012 rev.001 fig. 34 wp high time t high : wp fig. 33 wp setup time t su: wp fig. 32 wp hold time t hd :wp typical performance curves \ continued 0 0.2 0.4 0.6 0.8 1 1.2 0123456 supply voltage: vcc(v) wp data hold time: t hd:wp (s) spec ta=-40 ta= 25 ta= 85 -0.3 -0.2 -0.1 0 0.1 0.2 0123456 supply voltage: vcc(v) wp data set up time: t su:wp (s) spec ta=-40 ta= 25 ta= 85 0 0.2 0.4 0.6 0.8 1 1.2 0123456 supply voltage: vcc(v) wp efective time: t high:wp ( s) spec ta=-40 ta= 25 ta= 85 14/34 datasheet d a t a s h e e t BR24G32-3A ? 2012 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100050 -1-2 15.may.2012 rev.001 i 2 c bus communication i 2 c bus data communication i 2 c bus data communication starts by start condition input, and en ds by stop condition input. data is always 8bit long, and acknowledge is always required after each byte. i 2 c bus carries out data transmission with plural devices connected by 2 communication lines of serial data (sda) and serial clock (scl). among devices, there are ?master? that generates clock and control communication start and end, and ?slave? that is controlled by address peculiar to devices. eeprom becomes ?s lave?. and the device that out puts data to bus during data communication is called ?transmitter?, and the devic e that receives data is called ?receiver?. start condition (start bit recognition) ? before executing each command, start condition (start bit) where sda goes from 'high' down to 'low' when scl is 'high' is necessary. ? this ic always detects whether sda and scl are in start conditi on (start bit) or not, therefor e, unless this confdition is satisfied, any command is executed. stop condition (stop bit recongnition) ? each command can be ended by sda rising from 'low' to 'high' when stop condition (stop bit), namely, scl is 'high' acknowledge (ack) signal ? this acknowledge (ack) signal is a software rule to show whether data transfer has been made normally or not. in master and slave, the device ( -com at slave address input of write co mmand, read command, and this ic at data output of read command) at the transmitter (sending) side releases the bus after output of 8bit data. ? the device (this ic at slave address in put of write command, read command, and -com at data output of read command) at the receiver (receiving) side sets sda 'low ' during 9 clock cycles, and outputs acknowledge signal (ack signal) showing that it has received the 8bit data. ? this ic, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ack signal) 'low'. ? each write action outputs acknowledge signal (ack signal) 'l ow', at receiving 8bit data (word address and write data). ? each read action outputs 8bit data (read data), and detects acknowledge signal (ack signal) 'low'. when acknowledge signal (ack signal) is detected, and stop c ondition is not sent from the master ( -com) side, this ic continues data output. when acknowledge signal (ack signal) is not detected, this ic stops data transfer, and recognizes stop cindition (stop bit), and ends read action. and this ic gets in status. device addressing ? output slave address after start condition from master. ? the significant 4 bits of slave address are used for recognizing a device type. the device code of this ic is fixed to '1010'. ? next slave addresses (a2 a1 a0 --- device address) are for se lecting devices, and plural on es can be used on a same bus according to the number of device addresses. ? the most insignificant bit (r/w --- read / write) of sl ave address is used for designating write or read action, and is as shown below. setting r / w DD to 0 ------- write (setting 0 to word address setting of random read) setting r / w DD to 1 ------- read type slave address maximum number of connected buses BR24G32-3A 1 0 1 0 a2 a1 a0 r/ w DD 8 89 89 89 s p condition condition ack stop ack data data addres s start r/w ack 1-7 sda scl 1-7 1-7 fig.35 data transfer timing 15/34 datasheet d a t a s h e e t BR24G32-3A ? 2012 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100050 -1-2 15.may.2012 rev.001 write command write cycle ? arbitrary data is written to eeprom. when to write only 1 byte, byte write is normally used, and when to write continuous data of 2 bytes or more, simultaneous write is possible by page write cycle. the maximum number of write bytes is specified per device of each capacity. up to 32 arbitrary bytes can be written. ? during internal write execution, all input comm ands are ignored, therefore ack is not sent back. ? data is written to the address designated by word address (n-th address) ? by issuing stop bit after 8bit data input, write to memory cell inside starts. ? when internal write is started, command is not accepted for twr (5ms at maximum). ? by page write cycle, the following can be written in bulk : up to 32byte and when data of the maximum bytes or higher is sent, data from the first byte is overwritten. (refer to "internal address increment" of "notes on page write cycle" in p16.) ? as for page write cycle of BR24G32-3A, after the significant 7 bits of word address is designated arbitrarily, by continuing data input of 2 bytes or more , the address of insignificant 5 bits is incremented internally, and data up to 32 bytes can be written. a1 a2 wa 14 1 1 0 0 w r i t e s t a r t r / w s t o p 1st word address data slave address a0 d0 a c k sda line a c k a c k wa 0 a c k 2nd word address d7 *1 wa 15 wa 13 wa 12 wa 11 *1 wa12 to wa15 become don't care. fig.36 byte write cycle fig.37 page write cycle *1 wa12 to wa15 become don't care. w r i t e s t a r t r / w a c k s t o p 1st word address(n) sda line a c k a c k data(n+31) a c k slave address 1 0 0 0 1 0 a0 a1 a2 wa 14 d0 *1 data(n) d0 d7 a c k 2nd word address(n) wa 0 wa 15 wa 13 wa 12 wa 11 16/34 datasheet d a t a s h e e t BR24G32-3A ? 2012 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100050 -1-2 15.may.2012 rev.001 notes on write cycle continuous input list of numbers of page write number of pages 32byte product number BR24G32-3A the above numbers are maximum bytes for respective types. any bytes below these can be written. in the case BR24G32-3A, 1 page=32bytes, but the page write cycle time is 5ms at maximum for 32byte bulk write. it does not stand 5ms at maximum 32byte=160ms(max.) internal address increment page write mode write protect (wp) terminal ? write protect (wp) function when wp terminal is set vcc (h level), data rewrite of all addresses is prohibited. when it is set gnd (l level), data rewrite of all address is enabled. be sure to connect this terminal to vcc or gnd, or control it to h level or l level. do not use it open. in the case of use it as an rom, it is re commended to connect it to pull up or vcc. at extremely low voltage at power on / off, by setti ng the wp terminal 'h', mistake write can be prevented. for example, when it is started from address 1eh, therefore, increment is made as below, 1eh 1fh 00h 01h ??? which please note. 1eh ??? 1e in hexadecimal, therefore, 00011110 becomes a binary number. wa7wa6wa5wa4wa3wa2wa1wa0 00000000 00000001 00000010 0 0011110 0 0011111 0 0000000 incremen t 1eh significant bit is fixed. no digit up 17/34 datasheet d a t a s h e e t BR24G32-3A ? 2012 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100050 -1-2 15.may.2012 rev.001 read command read cycle data of eeprom is read. in read cycle, there are random read cycle and current read cycle. random read cycle is a command to read data by designating address, and is used generally. current read cycle is a command to read data of internal add ress register without designating address, and is used when to verify just after write cycle. in both the read cycles, sequential read cycle is available, and the next address data can be read in succession. ? in random read cycle, data of designated word address can be read. ? when the command just before current read cycle is random read cycle, current read cycle (each including sequential read cycle), data of incremented last read address (n)-t h address, i.e., data of t he (n+1)-th address is output. ? when ack signal 'low' after d0 is detected, an d stop condition is not sent from master ( -com) side, the next address data can be read in succession. ? read cycle is ended by stop condition where 'h' is input to ack signal after d0 and sda signal is started at scl signal 'h' . ? when 'h' is not input to ack signal after d0, seque ntial read gets in, and the next data is output. therefore, read command cycle cannot be ended. when to end read command cycl e, be sure input stop condition to input 'h' to ack signal after d0, and to start sda at scl signal 'h'. ? sequential read is ended by stop condition w here 'h' is input to ack signal after arbitrary d0 and sda is started at scl signal 'h'. w r i t e s t a r t r / w a c k s t o p 1st word address? sda line a c k a c k data(n) a c k slave address 1 0 0 1 a0 a1 a2 wa 14 d7 d0 2nd word address? a c k s t a r t slave address 1 0 0 1 a2 a1 r / w r e a d a0 wa 0 *1 wa 15 wa 13 wa 12 wa 11 fig.38 random read cycle *1 wa12 to wa15 become don?t care. s t a r t s t o p sda line a c k data(n) a c k slave address 10 0 1 a0 a1 a2 d0 d7 r / w r e a d fig.39 current read cycle r e a d s t a r t r / w a c k s t o p data(n) sda line a c k a c k data(n+x) a c k slave address 10 0 1 a0 a1 a2 d0 d7 d0 d7 fig.40 sequential read cycle (in the case of current read cycle) 18/34 datasheet d a t a s h e e t BR24G32-3A ? 2012 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100050 -1-2 15.may.2012 rev.001 software reset software reset is executed when to avoid malfunction after power on, and to reset during command input. software reset has several kinds, and 3 kinds of them are shown in the figure below. (refer to fig. 41-(a), fig.41-(b), fig.41-(c).) in dummy clock input area, release the sda bus ('h' by pull up). in dummy clock area, ack output and read data '0' (both 'l' level) may be output from eeprom, therefore, if 'h' is input forcibly, output may conflic t and over current may flow, leading to instantaneous power failure of system power source or influence upon devices. acknowledge polling during internal write execution, all input commands are ignored , therefore ack is not sent ba ck. during internal automatic write execution after write cycle input, next command (slave addr ess) is sent, and if the first ack signal sends back 'l', then it means end of write action, while if it sends back 'h', it means now in writing. by us e of acknowledge polling, next command can be executed without waiting for twr = 5ms. when to write continuously, r/w = 0, when to carry out current read cycle after write, slave address r/w = 1 is sent, and if ack signal sends back 'l', then execute word address input and data output and so forth. 1 2 13 14 scl dummy clock14 start2 scl fig.41-(a) the case of dummy clock 14 +start+start+ command input start command from start input. 2 1 8 9 dummy clock 9 start fig.41-(b) the case of start + dummy clock 9 +start+ command input start normal command normal command normal command normal command start 9 sda sda scl sd 1 2 3 8 9 7 fig.41-(c) start9+ command input normal command normal command sda slave address word address s t a r t first write command a c k h a c k l slave address slave address slave address data write command during internal write, ack = high is sent back. after completion of internal write, ack=low is sent back, so input next word address and data in succession. twr twr second write command s t a r t s t a r t s t a r t s t a r t s t o p s t o p a c k h a c k h a c k l a c k l fig.42 case to continuously write by acknowledge polling 19/34 datasheet d a t a s h e e t BR24G32-3A ? 2012 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100050 -1-2 15.may.2012 rev.001 wp valid timing (write cancel) wp is usually fixed to 'h' or 'l', but when wp is used to c ancel write cycle and so forth, pay attention to the following wp valid timing. during write cycle execution, in cancel valid area, by setting wp='h', write cycle can be cancelled. in both byte write cycle and page write cycle, the area fr om the first start condition of command to the rise of clock to taken in d0 of data(in page write cycle, the first byte data) is cancel invalid area. wp input in this area becomes don't care. the area from the rise of scl to take in d0 to input the stop condition is cancel valid area. and, after execution of forced end by wp, standby status gets in. command cancel by start condition and stop condition during command input, by continuously inputting start condition and stop condition, command can be cancelled. (fig.44) however, in ack output area and during data read, sda bus may output 'l', and in this case, start condition and stop condition cannot be input, so reset is not available. therefore, execute software reset. and when command is cancelled by start, stop condition, during random read c ycle, sequential read cycle, or current read cycle, internal setting address is not determined, therefore, it is not possible to carry out current read cycle in succession. when to carry out read cycle in succession, carry out random read cycle. ? rise of d0 taken clock scl d0 ack enlarged view scl sda ack d0 ? rise of sda sda wp wp cancel invalid area wp cancel valid area data is not written. fig.43 wp valid timing slave address d7 d6 d5 d4 d3 d2 d1 d0 data twr sda d1 s t a r t a c k l a c k l a c k l a c k l s t o p word address fig.44 case of cancel by start, st op condition during slave address input scl sda 1 1 0 0 start condition stop condition enlarged view wp cancel invalid area 20/34 datasheet d a t a s h e e t BR24G32-3A ? 2012 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100050 -1-2 15.may.2012 rev.001 i/o peripheral circuit pull up resistance of sda terminal sda is nmos open drain, so requires pull up resistance. as for this resistance value (r pu ), select an appropriate value to this resistance value from microcontroller v il , i l , and v ol -i ol characteristics of this ic. if r pu is large, action frequency is limited. the smaller the r pu , the larger the consumption current at action. maximum value of r pu the maximum value of r pu is determined by the following factors. sda rise time to be determined by the capacitance (cbus) of bus line of r pu and sda should be tr or below. and ac timing should be satisfied even when sda rise time is late. the bus electric potential a to be determined by input leak total (i l ) of device connected to bus at output of 'h' to sda bus and r pu should sufficiently secure the input 'h' level (v ih ) of microcontroller and eeprom including recommended noise margin 0.2vcc. vcc ilrpu 0.2 vcc R vih r pu Q 0.8v cc v ih i l ex.) vcc =3v il=10 a vih=0.7 vcc from Q 30 k ? r pu Q 0.83 0.73 1010 -6 minimum value of r pu the minimum value of r pu is determined by the following factors. when ic outputs low, it should be satisfied that v olmax =0.4v and i olmax =3ma. volmax=0.4v should secure the input 'l' level (v il ) of microcontroller and eeprom including recommended noise margin 0.1vcc. volmax Q vil 0.1 vcc ex.) vcc =3v, vol=0.4v, iol=3ma, microcontroller, eeprom v il =0.3vcc and vol=0.4 v vil=0.3 3 =0.9 v therefore, the condition is satisfied. pull up resistance of scl terminal when scl control is made at cmos output port, there is no need, but in the case there is timing where scl becomes 'hi-z', add a pull up resistance. as for the pull up resistance, one of several k to several ten k is recommended in consideration of drive performance of output port of microcontroller. i ol r pu R v cc v ol i ol v cc v o l r pu Q R 867 ?? r pu R 3 0.4 310 -3 from microcontroller r pu a sda terminal i l i l bus line capacity cbus fig.45 i/o circuit diagram br24gxx 21/34 datasheet d a t a s h e e t BR24G32-3A ? 2012 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100050 -1-2 15.may.2012 rev.001 cautions on microcontroller connection rs in i 2 c bus, it is recommended that sda port is of open drain in put/output. however, when to use cmos input / output of tri state to sda port, insert a series resistance rs betwe en the pull up resistance rpu an d the sda terminal of eeprom. this is controls over current that occurs when pmos of the microcontroller and nmos of eeprom are turned on simultaneously. rs also plays the role of protection of sd a terminal against surge. therefore, even when sda port is open drain input/output, rs can be used. maximum value of rs the maximum value of rs is determined by the following relations. sda rise time to be determined by the capacity (cbus) of bus line of rpu and sda should be tr or below. and ac timing should be satisfied even when sda rise time is late. the bus electric potential a to be determined by rpu and rs the moment when eeprom outputs 'l' to sda bus sufficiently secure the input 'l' level (v il ) of microcontroller including recommended noise margin 0.1vcc. minimum value of rs the minimum value of rs is determined by over current at bus collision. when over current flows, noises in power source line, and instantaneous power failure of power source ma y occur. when allowable over current is defined as i, the following relation must be satisfied. determine the allowable cu rrent in consideration of im pedance of power source line in set and so forth. set the over current to eeprom 10ma or below. r pu microcontroller r s eeprom fig.46 i/o circuit diagr am fig.47 input / output collision timing ack 'l' output of eeprom 'h' output of microcontroller over current flows to sda line by 'h' output of microcontroller and 'l' output of eeprom. scl sda microcontroller eeprom 'l'output r s r pu 'h' output over current i fig.49 i/o circuit diagram Q 1.67 k ? Q 0.33 0.4 0.13 2010 3 1.13 0.33 r s r pu 1.1v cc -v il ex. v cc =3v v il =0.3v cc v ol =0.4v r pu =20k r s Q v il v ol 0.1v cc (v cc v ol )r s +v ol +0.1v cc Q v il r pu +r s v cc r s v cc i R 300 ?? ex.) vcc=3v, i=10ma r s R 3 1010 -3 Q i r s R r pu micro controller r s eeprom i ol a bus line capacity cbus v ol v cc v il fig.48 i/o circuit diagram 22/34 datasheet d a t a s h e e t BR24G32-3A ? 2012 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100050 -1-2 15.may.2012 rev.001 i 2 c bus input / output circuit input (a0, a1, a2, scl, wp) input / output (sda) notes on power on at power on, in ic internal circuit and set, vcc rises through unstable low voltage area, and ic inside is not completely reset , and malfunction may occur. to prevent th is, functions of por circuit and lvcc circ uit are equipped. to assure the action, observe the following conditions at power on. 1. set sda = 'h' and scl ='l' or 'h? 2. start power source so as to satisfy the recommended conditions of t r , t off , and vbot for operating por circuit. toff tr vbot 0 v cc 3. set sda and scl so as not to become 'hi-z'. when the above conditions 1 and 2 cannot be obs erved, take the following countermeasures. a) in the case when the above condition 1 cannot be observed. when sda becomes 'l' at power on . control scl and sda as shown below, to make scl and sda, 'h' and 'h'. b) in the case when the above condition 2 cannot be observed. after power source becomes stable, execute software reset(p18). ) in the case when the above cond itions 1 and 2 cannot be observed. carry out a), and then carry out b). low voltage malfunction prevention function lvcc circuit prevents data rewrite action at low power, and prev ents wrong write. at lvcc voltage (typ. =1.2v) or below, it prevent data rewrite. vcc noise countermeasures bypass capacitor when noise or surge gets in the power source line, malfunction ma y occur, therefore, for removi ng these, it is recommended to attach a by pass capacitor (0.1 f) between ic vcc and gnd. at that moment, attach it as close to ic as possible. and, it is also recommended to attach a bypass capacitor between board vcc and gnd. fig.52 rise waveform diagram tlow tsu:dat tdh a fter vcc becomes stable scl v cc sda fi g .53 when scl= 'h' and sda= 'l' tsu:dat a fter vcc becomes stable fi g .54 when scl='l' and sda='l' recommended conditions of tr, toff,vbot tr toff vbot 10ms or belo w 10ms or larger 0.3v or below 100 or below 10ms or larger 0.2v or below fig.50 input pin circuit diagram fig.51 input / output pin circuit diagram 23/34 datasheet d a t a s h e e t BR24G32-3A ? 2012 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100050 -1-2 15.may.2012 rev.001 operational notes (1) described numeric values and data are design repres entative values, and the values are not guaranteed. (2) we believe that application circuit examples are recommendabl e, however, in actual use, confirm characteristics further sufficiently. in the case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static characteristics and transition characteristics and fluct uations of external parts and our lsi. (3) absolute maximum ratings if the absolute maximum ratings such as impressed voltage an d action temperature range and so forth are exceeded, lsi may be destructed. do not impress voltage and temperature exce eding the absolute maximum ratings. in the case of fear exceeding the absolute maximum ratings, take physical safety co untermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to lsi. (4) gnd electric potential set the voltage of gnd terminal lowest at any action condition. make sure that eac h terminal voltage is lower than that of gnd terminal. (5) terminal design in consideration of permissible loss in actual use condi tion, carry out heat design with sufficient margin. (6) terminal to terminal shortcircuit and wrong packaging when to package lsi onto a board, pay sufficient attenti on to lsi direction and displacement. wrong packaging may destruct lsi. and in the case of shortcircuit between lsi te rminals and terminals and power source, terminal and gnd owing to foreign matter, lsi may be destructed. (7) use in a strong electromagnetic field may cause malfunction, therefore, ev aluate design sufficiently. status of this document the japanese version of this document is fo rmal specification. a customer may use this translation version only for a reference to help reading the formal version. if there are any differences in translation version of this document formal version takes priority. 24/34 datasheet d a t a s h e e t BR24G32-3A ? 2012 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100050 -1-2 15.may.2012 rev.001 ordering information b r 2 4 g 3 2 x x x - 3 a x x bus type 24 : i 2 c operating temperature / operating voltage -40 to +85 / 1.7v to 5.5v process code packaging and forming specification e2 : embossed tape and reel (sop8,sop-j8, ssop-b8,tssop-b8, tssop-b8j) tr : embossed tape and reel (msop8, vson008x2030) none : tube (dip-t8) revision package blank f fv fvj nux : dip-t8 : sop8 : ssop-b8 : tssop-b8j : vson008x2030 fj fvt fvm : sop-j8 : tssop-b8 : msop8 capacity 32=32k 25/34 datasheet d a t a s h e e t BR24G32-3A ? 2012 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100050 -1-2 15.may.2012 rev.001 physical dimensions tape and reel information ? order quantity needs to be multiple of the minimum quantity. 26/34 datasheet d a t a s h e e t BR24G32-3A ? 2012 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100050 -1-2 15.may.2012 rev.001 ? order quantity needs to be multiple of the minimum quantity. 27/34 datasheet d a t a s h e e t BR24G32-3A ? 2012 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100050 -1-2 15.may.2012 rev.001 ? order quantity needs to be multiple of the minimum quantity. 28/34 datasheet d a t a s h e e t BR24G32-3A ? 2012 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100050 -1-2 15.may.2012 rev.001 ? order quantity needs to be multiple of the minimum quantity. 29/34 datasheet d a t a s h e e t BR24G32-3A ? 2012 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100050 -1-2 15.may.2012 rev.001 direction of feed reel ? order quantity needs to be multiple of the minimum quantity. 30/34 datasheet d a t a s h e e t BR24G32-3A ? 2012 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100050 -1-2 15.may.2012 rev.001 direction of feed reel ? order quantity needs to be multiple of the minimum quantity. 31/34 datasheet d a t a s h e e t BR24G32-3A ? 2012 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100050 -1-2 15.may.2012 rev.001 direction of feed reel ? order quantity needs to be multiple of the minimum quantity. 32/34 datasheet d a t a s h e e t BR24G32-3A ? 2012 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100050 -1-2 15.may.2012 rev.001 ? order quantity needs to be multiple of the minimum quantity. 33/34 datasheet d a t a s h e e t BR24G32-3A ? 2012 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100050 -1-2 15.may.2012 rev.001 marking diagrams sop8(top view) 4g32a part number marking lot numbe r 1pin mark sop-j8(top view) 4g32a part number marking lot number 1pin mark tssop-b8j(top view) 2a3 part number marking lot number 1pin mark 4g3 vson008x2030 (top view) 2a3 part number marking lot number 1pin mark 4g3 msop8(top view) 4gf part number marking lot number 1pin mark a tssop-b8(top view) 4g32a part number marking lot numbe r 1pin mark ssop-b8(top view) 4gfa part number marking lot number 1pin mark dip-t8 (top view) br24g32a part number marking lot number 34/34 datasheet d a t a s h e e t BR24G32-3A ? 2012 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100050 -1-2 15.may.2012 rev.001 revision history date revision changes 15.may.2012 001 new release datasheet d a t a s h e e t notice - rev.003 ? 2012 rohm co., ltd. all rights reserved. notice general precaution 1) before you use our products, you are requested to care fully read this document and fully understand its contents. rohm shall not be in any way responsible or liable for fa ilure, malfunction or accident arising from the use of any rohm?s products against warning, caution or note contained in this document. 2) all information contained in this document is current as of the issuing date and subjec t to change without any prior notice. before purchasing or using rohm?s products, please confirm the la test information with a rohm sales representative. precaution on using rohm products 1) our products are designed and manufactured for applicat ion in ordinary electronic equipments (such as av equipment, oa equipment, telecommunication equipment, home electroni c appliances, amusement equipment, etc.). if you intend to use our products in devices requiring extremel y high reliability (such as medical equipment, transport equipment, traffic equipment, aircraft/spacecra ft, nuclear power controllers, fuel c ontrollers, car equipment including car accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or serious damage to property (?specific applications?), please consult with the rohm sale s representative in advance. unless otherwise agreed in writing by rohm in advance, ro hm shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any ro hm?s products for specific applications. 2) rohm designs and manufactures its products subject to strict quality control system. however, semiconductor products can fail or malfunction at a certain rate. please be sure to implement, at your own responsibilities, adequate safety measures including but not limited to fail-safe desi gn against the physical injury, damage to any property, which a failure or malfunction of our products may cause. the following are examples of safety measures: [a] installation of protection circuits or other protective devices to improve system safety [b] installation of redundant circuits to reduce the impact of single or multiple circuit failure 3) our products are designed and manufactured for use under standard conditions and not under any special or extraordinary environments or conditio ns, as exemplified below. accordin gly, rohm shall not be in any way responsible or liable for any damages, expenses or losses arising from the use of an y rohm?s products under any special or extraordinary environments or conditions. if you intend to use our products under any special or extraordinary environments or conditions (as exemplified bel ow), your independent verification and confirmation of product performance, reliability, etc, prior to use, must be necessary: [a] use of our products in any types of liquid, incl uding water, oils, chemicals, and organic solvents [b] use of our products outdoors or in places where the products are exposed to direct sunlight or dust [c] use of our products in places where the products ar e exposed to sea wind or corrosive gases, including cl 2 , h 2 s, nh 3 , so 2 , and no 2 [d] use of our products in places where the products are exposed to static electricity or electromagnetic waves [e] use of our products in proximity to heat-producing components, plastic cords, or other flammable items [f] sealing or coating our products with resin or other coating materials [g] use of our products without cleaning residue of flux (ev en if you use no-clean type fluxes, cleaning residue of flux is recommended); or washing our products by using water or water-soluble cleaning agents for cleaning residue after soldering [h] use of the products in places subject to dew condensation 4) the products are not subjec t to radiation-proof design. 5) please verify and confirm characteristics of the final or mounted products in using the products. 6) in particular, if a transient load (a large amount of load applied in a short per iod of time, such as pulse) is applied, confirmation of performance characteristics after on-boar d mounting is strongly recomm ended. avoid applying power exceeding normal rated power; exceeding the power rating under steady-state loading c ondition may negatively affect product performance and reliability. 7) de-rate power dissipation (pd) depending on ambient temper ature (ta). when used in seal ed area, confirm the actual ambient temperature. 8) confirm that operation temperature is within t he specified range described in the product specification. 9) rohm shall not be in any way responsible or liable for fa ilure induced under deviant condi tion from what is defined in this document. datasheet d a t a s h e e t notice - rev.003 ? 2012 rohm co., ltd. all rights reserved. precaution for mounting / circuit board design 1) when a highly active halogenous (chlori ne, bromine, etc.) flux is used, the resi due of flux may negatively affect product performance and reliability. 2) in principle, the reflow soldering method must be used; if flow soldering method is preferred, please consult with the rohm representative in advance. for details, please refer to rohm mounting specification precautions regarding application examples and external circuits 1) if change is made to the constant of an external circuit, pl ease allow a sufficient margin c onsidering variations of the characteristics of the products and external components, including transient characteri stics, as well as static characteristics. 2) you agree that application notes, re ference designs, and associated data and in formation contained in this document are presented only as guidance for products use. theref ore, in case you use such information, you are solely responsible for it and you must exercise your own indepen dent verification and judgment in the use of such information contained in this document. rohm shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of such information. precaution for electrostatic this product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. please take proper caution in your manufacturing process and storage so that voltage exceeding t he products maximum rating will not be applied to products. please take special care under dry condit ion (e.g. grounding of human body / equipment / solder iron, isolation from charged objects, se tting of ionizer, friction prevention and temperature / humidity control). precaution for storage / transportation 1) product performance and soldered connections may deteriora te if the products are stor ed in the places where: [a] the products are exposed to sea winds or corros ive gases, including cl2, h2s, nh3, so2, and no2 [b] the temperature or humidity exceeds those recommended by rohm [c] the products are exposed to di rect sunshine or condensation [d] the products are exposed to high electrostatic 2) even under rohm recommended storage c ondition, solderability of products out of recommended storage time period may be degraded. it is strongly recommended to confirm sol derability before using products of which storage time is exceeding the recommended storage time period. 3) store / transport cartons in the co rrect direction, which is indicated on a carton with a symbol. otherwise bent leads may occur due to excessive stress applied when dropping of a carton. 4) use products within the specified time after opening a hum idity barrier bag. baking is required before using products of which storage time is exceeding the recommended storage time period. precaution for product label qr code printed on rohm products label is for rohm?s internal use only. precaution for disposition when disposing products please dispose them proper ly using an authorized industry waste company. precaution for foreign exchange and foreign trade act since our products might fall under cont rolled goods prescribed by the applicable foreign exchange and foreign trade act, please consult with rohm representative in case of export. precaution regarding intellectual property rights 1) all information and data including but not limited to application example contain ed in this document is for reference only. rohm does not warrant that foregoi ng information or data will not infringe any intellectual property rights or any other rights of any third party regarding such information or data. rohm shall not be in any way responsible or liable for infringement of any intellectual property rights or ot her damages arising from use of such information or data.: 2) no license, expressly or implied, is granted hereby under any intellectual property rights or other rights of rohm or any third parties with respect to the information contained in this document. datasheet d a t a s h e e t notice - rev.003 ? 2012 rohm co., ltd. all rights reserved. other precaution 1) the information contained in this document is provi ded on an ?as is? basis and rohm does not warrant that all information contained in this document is accurate and/or error-free. rohm shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or concerning such information. 2) this document may not be reprinted or reproduced, in whol e or in part, without prior written consent of rohm. 3) the products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written consent of rohm. 4) in no event shall you use in any way whatsoever the pr oducts and the related technical information contained in the products or this document for any military purposes, incl uding but not limited to, the development of mass-destruction weapons. 5) the proper names of companies or products described in this document are trademarks or registered trademarks of rohm, its affiliated companies or third parties. |
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